1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the formation of spacer elements used for the fabrication of field effect transistors, wherein the spacer elements may serve as an implantation mask and/or a silicidation mask.
2. Description of the Related Art
Presently, the vast majority of integrated circuits are manufactured on the basis of silicon with critical feature sizes in sophisticated devices on the order of 0.1 μm and even less. The fabrication of transistor elements representing the dominant components of complex circuits, such as microprocessors, storage devices and the like, typically require, among others, a controlled introduction of dopants into precisely defined silicon regions. The MOS circuit architecture, which is currently the preferred technology for forming logic circuitry owing to the superior performance with respect to power consumption, requires the formation of highly doped silicon regions with a weakly counter-doped or substantially undoped channel region disposed therebetween, wherein the conductivity of the channel region is controlled by an electric field generated by applying a control voltage to a gate electrode located in the vicinity of the channel region and separated therefrom by a gate insulation layer. Hence, a reduction in size of the transistor element necessitates the reduction of the distance between the highly doped silicon regions. This distance represents an important design criterion and is also referred to as the “channel length.” In currently favored CMOS technologies, the gate electrode is patterned prior to the formation of the highly doped silicon regions, also referred to as “drain region and source region,” to obtain the transistor geometry, i.e., the spatial relationship between the gate electrode, the drain region and the source region, in a self-aligned manner. Reducing the channel length therefore also requires a corresponding reduction of the size of the gate electrode. Generally, the gate electrode may be considered, at least partially, as a line-like circuit feature, the width of which is related to the corresponding channel length, which is thus also referred to as “gate length.”
Since the formation of the transistor elements, especially the creation of an appropriately shaped dopant profile in the drain and source regions, requires a plurality of high temperature processes for activating the dopants and for partially curing implantation-induced lattice damage, polysilicon is the presently preferred material for the gate electrode due to the superior and well-understood characteristics of the silicon/silicon dioxide interface, as silicon dioxide is frequently used in forming the gate insulation layer which separates the channel region from the gate electrode. Although the provision of the polysilicon gate electrode prior to the formation of the drain and source regions assures a self-aligned transistor geometry, it nevertheless turns out that complex, precisely-defined dopant profiles in the lateral direction are necessary to provide the required transistor performance of extremely scaled transistor devices. For this reason, so-called “sidewall spacers” or, briefly, “spacers” are typically formed on sidewalls of the gate electrode, which may be considered as dielectric extensions of the gate electrode. Hence, the spacers correspondingly modify the lateral dimensions of the gate electrode acting as an implantation mask during the implantation sequences for creating the required dopant profile. Since the dimensions of the sidewall spacers substantially determine the dopant profile obtained after implantation, the necessity for highly complex lateral dopant profiles also calls for advanced spacer formation techniques, in which sophisticated deposition and etch processes have to be applied to achieve the required dopant profile as implanted. Usually, sophisticated MOS transistor devices require the sequential formation of two or more sidewall spacers, whereby, after completion of each respective spacer, an implantation process is performed wherein the respective spacers in combination with the gate electrode serve as temporary implantation masks. Hence, a uniform and reliable spacer technology is required to provide a uniform transistor performance.
Due to the continuous decrease in feature sizes, the channel length and thus the gate length of the transistor devices also have to be decreased, thereby reducing the conductivity of the gate electrode owing to a reduced cross-sectional area and a disproportional increase of dopant depletion in the gate electrode. Moreover, the contact and sheet resistivity of the drain and source regions also increase as feature sizes are scaled down. The reduction in conductivity of the gate electrode and the drain and source regions is typically counteracted by forming a highly conductive metal silicide in the gate electrode and the drain and source regions. During the silicidation process, the sidewall spacers also serve as a reaction mask, enabling a reaction of the metal with underlying silicon material, but substantially preventing a silicide formation within the spacers, thereby assuring a self-aligned silicide formation. In recent developments, the amount of silicide formed in the gate electrode has been increased by recessing the sidewall spacers to expose an increased amount of the surface of the gate electrode, thereby enabling the formation of an increased metal silicide portion. However, recessing the sidewall spacers is accompanied by certain issues, as will be described with reference to FIGS. 1a–1c in more detail.
FIG. 1a schematically shows a cross-sectional view of a transistor element 100 in an advanced manufacturing stage. The transistor element 100 comprises a substrate 101, which may represent a silicon substrate or a silicon-on-insulator (SOI) substrate having formed thereon a silicon region 102, which is enclosed by an isolation structure 103, for instance provided in the form of a trench isolation structure. The silicon region 102 comprises highly doped drain and source regions, which are represented by an extension region 108 and a corresponding deeply doped region 109, which, for convenience, is referred to as drain region or source region. The drain and source regions 109 and the extension regions 108 are separated in a transistor length direction, i.e., in FIG. 1a in the horizontal direction, by a channel region 110, which is typically lightly doped with a dopant of an opposite conductivity type compared to the extension regions and drain and source regions 108, 109. A gate electrode 104, comprised of polysilicon, is formed above the silicon region 102 and is separated therefrom by a gate insulation layer 105, which may be comprised of silicon dioxide, silicon oxynitride, silicon nitride and the like. Moreover, a silicon dioxide liner 106 is formed on the gate electrode 104 and on surface portions of the silicon region 102, which are not covered by the gate electrode 104. Sidewall spacers 107, comprised of silicon nitride, are shown in an intermediate state during an etch procedure indicated as 111.
A typical process flow for forming the transistor element 100 as shown in FIG. 1a may comprise the following processes. After forming the isolation structure 103 by sophisticated photolithography, etch and deposition techniques, when trench isolations are considered, implantation cycles may be performed to establish a required vertical dopant profile, for instance required for the threshold adjustment and the like, within the silicon region 102. Thereafter, the gate insulation layer 105 and the gate electrode 104 may be formed by, for example, sophisticated oxidation techniques and/or deposition techniques, and by depositing a polysilicon layer by low pressure chemical vapor deposition, respectively, and by subsequently patterning the resulting layer stack by well-established photolithography, trim etch techniques and anisotropic etch processes.
Thereafter, the extension regions 108 may be formed by a corresponding implantation sequence using the gate electrode 104 as an implantation mask. Next, the silicon dioxide liner 106 may be formed by plasma enhanced chemical vapor deposition (PECVD), wherein a thickness of the silicon dioxide liner 106 is selected to serve, in combination with the sidewall spacer 107, as an extension of the gate electrode 104 during a subsequent implantation sequence for forming the drain and source regions 109. The silicon dioxide liner 106 is required as an etch stop layer during the anisotropic etch process 111 for patterning the sidewall spacers 107. Thereafter, a silicon nitride layer is deposited by PECVD, wherein a thickness of the layer substantially determines, in combination with the thickness of the silicon dioxide liner 106, the total width of an implantation mask defined by the gate electrode 104 and the sidewall spacer 107, including the silicon dioxide liner 106.
As previously discussed, the shrinkage of the gate length, i.e., the horizontal extension of the gate electrode 104 in FIG. 1a, and the reduction of the thickness of the gate insulation layer 105 associated therewith requires a thorough profiling of the dopant concentration in the vicinity of the edge of the gate electrode 104 in view of desired high conductivity and with respect to control of the resulting electric field prevailing during the operation of the transistor element 100. Consequently, controlling the thickness of the silicon dioxide liner 106 and of the silicon nitride layer used for forming the sidewall spacers 107 is an important aspect in obtaining substantially uniform transistor characteristics across a single die and across the entire substrate 101. For instance, the formation of a thin conformal layer, such as the silicon dioxide liner 106, may be influenced by the type of pattern to which the transistor element 100 belongs. That is, in substrate areas or die areas of high pattern density, i.e., with a high number of gate electrodes per unit area, the deposition kinetics may be different from die or substrate areas having formed thereon substantially isolated gate electrodes, i.e., gate electrodes spaced apart from neighboring line elements by a distance that is many times the gate length. For this reason and owing to typical global across-substrate thickness variations in the deposition process of approximately 1.5% across the entire substrate area, the transistor performance may vary accordingly, as the dopant profiles 108 and 109 may exhibit a corresponding variation owing to a varying width of the implantation mask, i.e., the gate electrode 104 plus the spacer 107 and the liner 106, during the implantation processes.
After depositing the silicon nitride layer, the anisotropic etch process 111 is performed to remove excess material, thereby forming the sidewall spacers 107. During the etch process 111, the silicon dioxide liner 106 protects horizontal device portions exposed to the etch front of the plasma etch process 111. As previously discussed, in later manufacturing stages, a metal silicide is formed in the gate electrode 104 and the drain and source regions 109. Since a size reduction of the gate electrode 104 is typically associated with a reduction of conductivity, it is desirable to convert as much of the polysilicon into a highly conductive metal silicide as possible, thereby compensating the reduced cross-sectional area and the enhanced dopant depletion in the gate electrode 104. Consequently, in sophisticated transistor devices, the anisotropic etch process 111 is continued to expose an upper sidewall portion of the gate electrode 104, which may then serve as an increased diffusion path during the conversion of silicon into metal silicide.
FIG. 1b schematically shows the device 100 after completion of the anisotropic etch process 111, thereby forming a recessed sidewall spacer 107a. Moreover, exposed portions of the silicon dioxide liner 106 are substantially removed, at least from horizontal surface portions, while residues 112 of the silicon dioxide liner 106 may still be present at upper sidewall portions 104a of the gate electrode 104, exposed by the recessed sidewall spacers 107a. 
In a typical conventional process flow, the silicon dioxide liner 106 is removed by a wet chemical process, for instance using (diluted) hydrofluoric acid (HF), followed by a sputter cleaning process prior to the sputter deposition of a refractory metal. However, owing to the highly directional nature of the sputter cleaning process, the silicon dioxide liner 106 may not be completely removed prior to the subsequent metal deposition. Consequently, the residues 112 may block a certain area of diffusion paths during a chemical reaction between the refractory metal and the polysilicon of the gate electrode 104.
FIG. 1c schematically shows the situation during the formation of metal silicide on top of the gate electrode 104 in more detail. A layer 113 comprised of a refractory metal, such as cobalt, nickel and the like, is formed over the gate electrode 104, and, according to a typical process flow, over the drain and source regions 109, wherein substantially non-hindered diffusion paths 114 are provided for the refractory metal of the layer 113, while at locations including the oxide residues 112, diffusion paths 115 are substantially blocked for the conversion of the refractory metal in the layer 113 into a highly conductive metal silicide. Consequently, the amount of metal silicide, and thus the finally achieved conductivity of the gate electrode 104, is reduced compared to that which is intended by providing the recessed spacers 107a. Hence, further device scaling may be accompanied by a reduced gain of transistor performance owing to the reduced gate conductivity and thickness variations of the oxide liner 106 used for patterning the spacers 107a. 
In view of the above-explained situation, there exists a need for an improved technique for forming recessed sidewalls spacers that enables enhancement of the conductivity of the gate electrode while maintaining a high degree of compatibility with the conventional process flow.